In advanced technology nodes of integrated circuit industry, high k dielectric material and metal are adopted to form a gate stack of a field-effect transistor (FET) such as a metal-oxide-semiconductor field-effect transistors (MOSFETs). Metal gate stacks are often planarized, such as by chemical-mechanical polishing (CMP), and then covered with a contact etch-stop layer (CESL). Additional processing operations are then performed, including forming an interlayer dielectric (ILD) above the metal gate stack, and then patterning and forming a contact through the ILD. As a result of these additional processing operations, it has been found that damage sometimes occurs to the metal gate stacks. For example, an acid solvent can reach the metal gate stack and adversely affect the gate stack, such as by forming a void or other defect. It is desired to maintain the integrity of the metal gate stack throughout the various processes.
It is also desired to maintain high production efficiency, adding to maintain or reduce the number of processing operations and processing tools used to fabricate devices such as MOSFETs. Therefore, an improved interface for a metal gate stack and a method making the same are needed to address the issues identified above.